Not Applicable.
The present specification relates generally to fabrication of integrated circuits (ICs). More specifically, the present specification relates to photolithographic techniques for fabricating features on ICs. More specifically yet, the present specification relates to a system and method of reducing a dimension of a feature in a photolithographic patterning process.
The semiconductor industry has a need to manufacture integrated circuits (ICs) with higher and higher densities of devices on a smaller chip area to achieve greater functionality and to reduce manufacturing costs. This desire for large-scale integration has led to a continued shrinking of the circuit dimensions and features of the devices.
The ability to reduce the sizes of structures, such as gates in field effect transistors (FETs), is driven by lithographic technology which is, in turn, dependent upon the wavelength of light used to expose the photoresist. In current commercial fabrication processes, optical devices expose the photoresist using light having a wavelength of 248 nm (nanometers). Research and development laboratories are experimenting with the 193 nm wavelength to reduce the size of structures. Further, advanced lithographic technologies are being developed that utilize radiation having a wavelength of 157 nm and even shorter wavelengths, such as those used in Extreme Ultra-Violet (EUV) lithography (e.g., 13 nm).
One challenge facing lithographic technology is fabricating features having a critical dimension (CD) below 100 nm. All steps of the photolithographic techniques currently employed must be improved to achieve the further reduction in feature size. One step which must be improved is the patterning of photoresist on the substrate.
In a conventional technique, light is exposed through a binary mask to a photoresist layer on a layer of material. The photoresist layer may be either a positive or a negative photoresist and can be a silicon-containing, dry-developed resist. In the case of a positive photoresist, the light causes a photochemical reaction in the photoresist. The photoresist is removable with a developer solution at the portions of the photoresist that are exposed through the mask. The photoresist is developed to clear away these portions, whereby a photoresist feature remains on the layer of material. An integrated circuit feature, such as a gate, via, or interconnect, is then etched into the layer of material, and the remaining photoresist is removed.
The linewidth of the integrated circuit feature is limited using the conventional process. For example, aberrations, focus, and proximity effects in the use of light limit the ability to fabricate features having reduced linewidth. Using a 248 nm wavelength light source, the minimum printed feature linewidth is between 300 and 150 nm, using conventional techniques.
Accordingly, what is needed is a method of reducing the linewidth of features of an integrated circuit. Further, what is needed is a system for and method of reducing the linewidth of photoresist features. Further still, what is needed is such a method which is simple and cost-effective to implement. The teachings hereinbelow extend to those embodiments which fall within the scope of the appended claims, regardless of whether they accomplish one or more of the above-mentioned needs.
According to an exemplary embodiment, a method of fabricating a feature of an integrated circuit in a layer of material includes providing a layer of photoresist over the layer of material and exposing the layer of photoresist to a source of radiation to form an aperture therein. The aperture has a wall. The method also includes providing a self-assembled monolayer on at least a portion of the wall, wherein the self-assembled monolayer masks a portion of the layer of material, and etching the layer of material to form a feature. The self-assembled monolayer prevents the portion of the layer of material from being etched.
According to another exemplary embodiment, an integrated circuit has a hole in a layer of material. The hole is manufactured by the steps of providing a layer of photoresist over the layer of material, exposing the layer of photoresist to a source of radiation to form an aperture therein, adsorbing a self-assembled monolayer to at least a portion of the aperture surface, and etching the layer of material through the aperture to form a hole in the layer of material.
According to yet another exemplary embodiment, a method of masking and etching a layer of material on a substrate includes providing a layer of material over the substrate, providing a photoresist layer having an aperture therein over the layer of material, and adsorbing a self-assembled monolayer to the wall of the aperture. The self-assembled monolayer has a structure and chemical composition suitable for preventing a portion of the layer of material from being substantially affected by an etching process. The method can also include etching the layer of material with the etching process.